The invention is directed to a more efficient approach for implementing layout, placement, and routing of integrated circuit designs.
A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer.
The various components of an integrated circuit are initially defined by their functional operations and relevant inputs and outputs. From the HDL or other high level description, the actual logic cell implementation is typically determined by logic synthesis, which converts the functional description of the circuit into a specific circuit implementation. The logic cells are then “placed” (i.e., given specific coordinate locations in the circuit layout) and “routed” (i.e., wired or connected together according to the designer's circuit definitions). The placement and routing software routines generally accept as their input a netlist that has been generated by the logic synthesis process. This netlist identifies the specific logic cell instances from a target standard cell library, and describes the specific cell-to-cell connectivity.
Conventionally, Physical Verification (PV) is one of the final steps that is performed before releasing an IC design to manufacturing. A key component of conventional PV includes the process of Design Rule Check (DRC) to ensure that the design abides by all of the detailed rules and parameters that the foundry specifies for its manufacturing process. Violating a single foundry rule can result in a silicon product that does not work for its intended purpose. Therefore, it is critical in conventional tools that thorough DRC processing is performed before finalizing an IC design.
FIG. 1 shows a flowchart of a conventional process for performing electronic design using DRC. The process begins with the completion of a layout using a place and route tool (102). Once the layout is complete, DRC processing is performed on the layout to identify any rule violations that may exist within the layout (104).
The DRC produces either a “violation” or “no violation” result for each rule that is checked against the layout. Essentially, each rule is associated with one or more parameter values that is checked for compliance with the rule. The DRC process will check those parameters to produce a simple “yes” or “no” answer as to whether the rule has been violated. For example, a very common rule is to check for minimum spacing between objects in a layout. DRC processing will determine whether all objects meet the minimum spacing requirements. If all objects meet the spacing requirements, then the layout meet the rules requirement for spacing. If any objects are spaced closer together than the minimum spacing requirement, then the rules violation will be identified.
If there are any rules violations (106), then the process will modify the layout to correct the rules violation (102). If no rules violations have been identified, then the IC design is passed to the next design stage for manufacturing (108).
DRC tools typically read and manipulate a design database which stores information about device geometries and connectivity. Because compliance with design rules generally constitutes the gating factor between one stage of the design and the next, DRC tools are typically executed multiple times during the evolution of the design and contribute significantly to the project's critical path. Therefore, reducing DRC tool execution time makes a major contribution to the reduction of overall design cycle times.
As the quantity of data in modern IC designs become larger and larger over time, the execution time required to process DRC tools upon these IC designs also becomes greater. The goal of reducing PV tool execution time is in sharp tension with many modern IC designs being produced by electronics companies that are constantly increasing in complexity and number of transistors. The more transistors and other structures on an IC design, the greater amounts of time that is normally needed to perform DRC processing. This problem is exacerbated by constantly improving IC manufacturing technologies that can create IC chips at ever-smaller feature sizes, which allows increasingly greater quantities of transistors to be placed within the same chip area, as well resulting in more complex physical and lithographic effects during manufacture.
In addition, DRC rules often contain design constraints that are much more limiting than are needed for any particular design or portion of a design. DRC rules are often set at the “lowest common denominator” level to ensure that most or all IC designs will properly operate. However, certain IC design may actually need parameters that are more or less cautious than other designs. Since DRC rules typically operate on an “all or nothing” basis, this means that many IC design may fail DRC processing even though they would function properly for intended purposes if manufactured.
Therefore, there is a need for an improved method and system for implementing IC designs that limits the amount of resources consumed by DRC processing.
The present invention is a method, system, and computer program product for model-based method for placement and routing. Models are used to guide the placement and routing of polygons on the IC layout. In effect, the parameters that are used for placement and routing are guided by the model data so that the layout can be formed with a high degree of manufacturability from the outset.